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1 data sheet switching products for additional information and latest specifications, see our website: www.triquint.com t r i q u i n t s e m i c o n d u c t o r , i n c . TQ8033 1.5 gbit/sec 64x33 expandable crosspoint switch features ? >1.5 gb/s/port data rate >50 gb/s aggregate bandwidth ? differential pecl data path with 64 inputs and 33 outputs ? non-blocking architecture supports broadcast and multicast operation ? data inputs internally biased for ac coupling ? low jitter and signal skew ? double-buffered configuration latches ? ttl configuration control inputs ? 304-pin bga package ? single +5v supply applications ? telecom/datacom switching including fibre channel and gigabit ethernet ? hubs and routers ? video switching including high-definition tv (hdtv) the TQ8033 is a non-blocking 64 x 33 digital crosspoint switch that supports data rates greater than 1.5 gigabits per second per channel. the TQ8033's non-blocking architecture allows any combination of output-to-input programming, supporting both broadcast and multicast applications. using 33 independent 64:1 multiplexers, each output channel can be programmed to any input without restriction or degradation of signal fidelity. the TQ8033's architecture is ideally suited for building larger switch arrays. by eliminating the need to "wire-or" or buss the outputs to interconnect multiple devices, the maximum system bandwidth and signal fidelity is achived. designed for use in high-performance / high-capacity switching applications, the TQ8033 data path is fully differential to minimize jitter, skew, and signal distortion. the data path interface levels are pecl and the configuration and control interface levels are ttl. the TQ8033 is the ideal switching solution for hdtv digital video, data communications (fibre channel and gigabit ethernet) and telecommunications applications. configure resetin load iadd(0:5) o add(0:4) monitor_ld 5:32 decoder 33 6-bit program latches 64 x 33 crosspoint switch matrix 33 6-bit configuration latches input buffers output buffers o 0 o32 66 d0?63 128 TQ8033
TQ8033 2 data sheet for additional information and latest specifications, see our website: www.triquint.com circuit description data inputs the 64 data input channels are differential pecl compatible. all inputs have a 2.5k w thevenin equivalent bias circuit which holds the dc bias at v dd -1.3 volts simplifying the design of applications requiring ac coupling. input signals must be properly terminated for maximum performance. terminate one side (true or complement) of any unused inputs to v tt . data outputs the 33 data output channels are differential pecl compatible and designed to be terminated to 50 w to v dd -2.0 volts. unused outputs can be left unterminated if desired in order to save power. control inputs the control inputs interface levels are ttl compatible. program registers the configuration data for each of the 33 data channels have two sets, or stages, of configuration storage registers. the first stage, known as the program register, stores a new set of input configurations prior to application to the switch core. the second stage, known as the configuration register, stores the current switch core configurations. the use of two stage configuration storage registers allows new input configurations to be loaded without disturbing the existing configuration. after the new input configurations have been loaded into the program registers, the configure input is asserted and the new configurations are applied to the switch core. to program the TQ8033, the address of the desired output port is applied to the inputs (oadd0:4; where 00000=o0 and 11111=o31). the address of the desired input port is applied to the inputs (iadd0:5; where 000000=i0 and 111111=i63). the new configuration is loaded into the program registers by asserting the load signal high. the data is latched when load is de-asserted. load should remain low and only be asserted for the time necessary to load the new configuration data. the process is repeated for each output port configuration. only the output ports which are to receive a new input port configuration need to be programmed. the new configurations are not applied to the switch core at this time and there is no disruption of the data flowing through the switch core. after the new configurations have been loaded into the program registers, the configure input is asserted and the data in the program registers is loaded into the configuration registers. the data is latched on the falling edge of configure. the switch core receives the new configuration as soon as configure is asserted. during the time the new configurations are being applied to the switch core, the integrity of the data on output ports which receive a new configuration is unknown for a period of tdcf from the time configure is asserted. if desired, the load and configure can be asserted simultaneously. in this mode, the new configuration will be applied to the switch core when load is asserted.
TQ8033 3 switching products data sheet for additional information and latest specifications, see our website: www.triquint.com programming the monitor port the 33rd output port, called the monitor port, is programmed in the same manner as the other 32 output ports with the exceptions that the load and output address inputs are ignored. to program the monitor port, apply the desired input port address to inputs (iadd0:5) and assert the monitor_ld input. like the other 32 output ports, the configure input is asserted to apply the new configuration to the switch core. reset programming the resetin is an active high input which sets all of the switch multiplexers to a defined configuration. there are three reset modes available when resetin is used in conjunction with configure and iadd5 inputs. the monitor port is reset to input d0 regardless of the state of configure or iadd5. mode 1 is broadcast operation. in this mode, the resetin signal clears all of the configuration registers immediately forcing all output ports to be connected to input port 0. the device will remain in the mode 1 reset state as long as the resetin input is asserted. modes 2 and 3 place the device into pass-through configuration. the mode is controlled by the assertion of configure immediately following the de-assertion of resetin and the state of input iadd5. mode 2, or low-order pass-through, is set with the assertion of configure with iadd5 input low. in this mode, inputs d0 to d31 are configured to outputs o0 to o31 respectively (d0 to o0, d1 to o1,,,d31 to o31). mode 3, or high-order pass-through, is set with the assertion of configure with iadd5 input high. in this mode, inputs d32 to d63 are configured to outputs o0 to o31 respectively (d32 to o0, d33 to o1,,,d63 to o31). reset configuration modes mode resetin configure** iadd5** reset configuration 1 1 0 x broadcast mode. all outputs programmed to input 0 2 1 1 0 low-order pass-through mode #1. 3 1 1 1 high-order pass-through mode #2. ** valid only when asserted immediately following de-assertion of resetin and prior to any new program cycles.
TQ8033 4 data sheet for additional information and latest specifications, see our website: www.triquint.com building switch arrays with the TQ8033 by eliminating the need to wire-or the outputs of multiple devices or to add additional switch elements to get the necessary routing channels, the TQ8033 offers the highest performance solution with the least number of devices for implementing larger array sizes. the 33rd output port provides an additional data channel for system data links or for diagnostics system monitoring of each switch element within the array. the following examples show how to interconnect multiple TQ8033 devices to create a 64x64 and a 128x128 switch array. 64x64 switch array to implement a 64x64 array (figure 2) , only two TQ8033 devices are required and the data passes through only one switch element. for applications with data rates less than one gigabit per second, a technique known as"fly-by" termination offers good signal fidelity with the minimum number of components. to implemement, both the input signal pairs (true and complement) are routed to both devices and then to the termination network at the end of the signal trace with the minimum number of trace discontinuities. to accomplish this, route the trace from the source device to the first TQ8033 input pad and then continue the signal trace from the input pads to the next device, and finally to the termination network. for applications at data rates above one gigabit per second, it is recommended to use a fan-out buffer to drive each TQ8033 input as shown in figure 3 . as with any high speed interconnect, careful attention to the impedance of the signal traces is very important. v tt 50 w 50 w TQ8033 TQ8033 d63 d0 o0 o31 o32 o63 figure 2. 64x64 array with "fly-by" termination figure 3. optional fan-out buffer for array expansion connect one driver output to each common TQ8033 input dn/ ndn
TQ8033 5 switching products data sheet for additional information and latest specifications, see our website: www.triquint.com 128x128 switch array to implement a 128x128 switch array, simply extend the design of the 64x64 switch array to include the additional devices. in this configuration, only 12 TQ8033 devices are required and the signal passes through only two switch stages. again, use fly-by interconnection or a fan-out buffer on input signals to connect multiple devices and the far-end termination network. larger switch arrays can be built by simply adding additional TQ8033 devices. TQ8033 64x33 crosspoint switch TQ8033 64x33 crosspoint switch TQ8033 64x33 crosspoint switch TQ8033 64x33 crosspoint switch TQ8033 64x33 crosspoint switch TQ8033 64x33 crosspoint switch TQ8033 64x33 crosspoint switch TQ8033 64x33 crosspoint switch TQ8033 64x33 crosspoint switch TQ8033 64x33 crosspoint switch TQ8033 64x33 crosspoint switch TQ8033 64x33 crosspoint switch d0-31 d32-63 d64-95 d96-127 64 64 64 64 64 64 32 32 32 32 d0-63 d64-127 monitor monitor monitor monitor monitor monitor monitor monitor monitor monitor monitor monitor 32 32 32 32 32 32 32 32 figure 4. 128x128 array
TQ8033 6 data sheet for additional information and latest specifications, see our website: www.triquint.com typical performance data rate: 1.5gb/s data pattern: 2 23-1 prbs case temperature: 0 c jitter: 54 ps pk-pk data rate: 1.5gb/s data pattern: 2 23-1 prbs case temperature: 85 c jitter: 56 ps pk-pk
TQ8033 7 switching products data sheet for additional information and latest specifications, see our website: www.triquint.com typical performance crosspint devices: 2 (cascaded) data rate: 1.5gb/s data pattern: 2 23-1 prbs case temperature: 85 c jitter: 110 ps pk-pk rise and fall time data rate: 1.5gb/s data pattern: 2 23-1 prbs case temperature: 85 c rise/fall time: 170/166 ps
TQ8033 8 data sheet for additional information and latest specifications, see our website: www.triquint.com table 1. dc characteristics pecl i/o 3,4 parameter notes/condition symbol minimum nominal maximum unit input common mode range v icom v dd C 1500 v dd C 1100 mv differential pk-pk input voltage swing (1, 2) d v in 800 2400 mv differential pk-pk output voltage swing (1, 2) d v out 1200 2200 mv output common mode range v ocom v dd -1500 v dd -1100 mv input capacitance c in 2.6 3.3 pf esd breakdown rating v esd 1000 v table 2. dc characteristicsttl i/o 3 parameter notes/condition symbol minimum nominal maximum unit input high voltage v ih 2.0 v dd v input low voltage v il 0 0.8 v input high current v ih(max) i ih 200 ua input low current v il(min) i il C400 C200 ua input capacitance c in 3.3 pf esd breakdown rating v esd 1000 v notes (tables 1 and 2): 1. defined as (2 x (| v true - v comp |)) 2. r load = 50 ohms to v tt = v dd C 2.0v. 3. specifications apply over recommended operating ranges. 4. inputs are internally dc-biased to v dd C 1.3v with 2.5k w thevenin input impedance for applicaitons requiring ac coupling. specifications subject to change without notice specifications
TQ8033 9 switching products data sheet for additional information and latest specifications, see our website: www.triquint.com table 3. ac characteristics parameter notes/condition symbol minimum nominal maximum unit maximum data rate/port 1.5 gb/s d0-63 minimum pulse width (1) t pw 500 ps o0-32 rise/fall time 20-80% (1) t r/f 250 ps channel propagation delay (mean) (1) t pd 2.5 ns ch-to-ch propagation delay skew (1) t skew 200 500 ps o0-32 jitter (2) t jitter 85 200 ps notes: 1. min. v oh to max v ol levels 2. crossing of (on) C (non) measured with 2 23 C 1 prbs, measured over extended time. figure 5. timing diagram table 4. timing specifications symbol parameter minimum maximum unit t sar[oadd] output address to load set-up time 1 ns t sar[iadd] input address to load set-up time 1 ns t har address to load hold time 2.5 ns t pwl min. load pulse width 2.5 ns t ldh load to configure delay 0 ns t pwc min. configure pulse width 7 ns t dcf configure to data valid 15 ns t ldl configure to load delay 3 ns tsar[oadd] tdcf tpwl tldh d (63:0) tpwc o (32:0) tsar[iadd] thar data valid tldl data not valid ** ** data valid on outputs with unchanged configurations input address [iadd5:0] output address [oadd4:0] configure load valid address valid address tpd
TQ8033 10 data sheet for additional information and latest specifications, see our website: www.triquint.com table 5. absolute maximum ratings 4 parameter condition symbol minimum nominal maximum unit storage temperature t store C65 150 c junction temperature t ch C65 150 c case temperature w/bias (1) t c 0 100 c supply voltage (2) v dd 0 7.0 v voltage to any input (2) v in C0.5 v dd + 0.5 v voltage to any output (2) v out C0.5 v dd + 0.5 v current to any input (2) i in C1.0 1.0 ma current from any output (2) i out 40.0 ma power dissipation of output (3) p out 50.0 mw notes: 1. tc is measured at case top. 2. all voltages are measured with respect to gnd (0v) and are continuous. 3. pout = (v dd C v out ) x i out . 4. absolute maximum ratings, as detailed in this table, are the ratings beyond which the devices performance may be impaired and/or permanent damage to the device may occur. table 6. recommended operating conditions 4 symbol parameter min typ max units notes t c case operating temperature 0 85 c 1, 3 v dd supply voltage 4.75 5.25 v i dd current positive supply 3 a v tt load termination supply voltage v dd C 2.0 v 2 r load output termination load resistance 50 w 2 q jc thermal resistance junction to case 2.2 c/w notes: 1. t c measured at case top. use of adequate heatsink is required. 2. the v tt and r load combination is subject to maximum output current and power restrictions. 3. contact the factory for extended temperature range applications. 4. functionality and/or adherence to electrical specifications is not implied when the device is subjected to conditions that e xceed, singularly or in combination, the operating range specified.
TQ8033 11 switching products data sheet for additional information and latest specifications, see our website: www.triquint.com figure 6. typical high speed measurement v dd gnd scope 50 w TQ8033 v dd pecl pecl gnd 50 w out - nout out nout out nout vbias pecl/ecl termination pecl/ecl termination ** pecl/ecl terminations available from cascade microtech model 523-0150 and picosecond pulse labs model 5623
TQ8033 12 data sheet for additional information and latest specifications, see our website: www.triquint.com figure 7. pinout bottom view table 7. pin descriptions signal type grid ref. description not connected b7, c1, c8, t3, u2, aa16, ab17 - do not connect - leave open vdd a1, a23, b2, b22, c3, c5, c19, c21, d3, d4, d6, d9, d12, d15, d18, d20, d21, f4, f20 j4, j20, m4, m20, r4, r20, v4, v20, w3, w21, y4, y6, y9, y12, y15, y18, y20, aa3, aa5, aa19, aa21, ab2, ab22, ac1, ac23 gnd a2, a6, a8, a9, a12, a15, a16, a18, a22, b1, b3, b21, b23, c2, c22, f1, f23, h1, h23, j1, j23, m1, m23, r1, r23, t1, t23, v1, v23, aa2, aa22, ab1, ab3, ab21, ab23, ac2, ac6, ac8, ac9, ac12, ac15, ac16, ac18, ac22 resetin ttl input e20 active high. reset loads program registers with default input. load ttl input c23 active high, loads input port data into the selected output port's program registers. output port definfed by oadd(0:4) configure ttl input d22 active high. transfers the data for all program registers into the second stage configure registers and into the switch core. monitor_ld ttl input e4 active high. directly loads the 33rd output port program register. the oadd(0:5) and load are not used to program this port. iadd0 ttl input e21 input address lsb. (d0= 000000, d63= 111111) iadd1 ttl input d23 input address. iadd2 ttl input e22 input address. iadd3 ttl input f21 input address. iadd4 ttl input g20 input address. iadd5 ttl input e23 input address msb. (continued on next page) a b c d e f g h j k l m n p r t u v w y aa ab ac 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 gnd vdd TQ8033 304-pin bga bottom view
TQ8033 13 switching products data sheet for additional information and latest specifications, see our website: www.triquint.com table 7. pin descriptions (cont.) signal type grid ref. description oadd0 ttl input f22 output address lsb. (o0=00000, o31= 11111) oadd1 ttl input g21 output address. oadd2 ttl input h20 output address. oadd3 ttl input g22 output address. oadd4 ttl input h21 output address msb. data inputs d0, nd0 pecl input c20, d19 high-speed input and complement. d1, nd1 pecl input a21, b20 high-speed input and complement. d2, nd2 pecl input a20, b19 high-speed input and complement. d3, nd3 pecl input c18, d17 high-speed input and complement. d4, nd4 pecl input a19, b18 high-speed input and complement. d5, nd5 pecl input c17, d16 high-speed input and complement. d6, nd6 pecl input b17, a17 high-speed input and complement. d7, nd7 pecl input c16, b16 high-speed input and complement. d8, nd8 pecl input c15, b15 high-speed input and complement. d9, nd9 pecl input d14, c14 high-speed input and complement. d10, nd10 pecl input b14, a14 high-speed input and complement. d11, nd11 pecl input d13, c13 high-speed input and complement. d12, nd12 pecl input b13, a13 high-speed input and complement. d13, nd13 pecl input c12, b12 high-speed input and complement. d14, nd14 pecl input a11, b11 high-speed input and complement. d15, nd15 pecl input c11, d11 high-speed input and complement. d16, nd16 pecl input a10, b10 high-speed input and complement. d17, nd17 pecl input c10, d10 high-speed input and complement. d18, nd18 pecl input b9, c9 high-speed input and complement. d19, nd19 pecl input b8, a7 high-speed input and complement. d20, nd20 pecl input d8, c7 high-speed input and complement. d21, nd21 pecl input b6, a5 high-speed input and complement. d22, nd22 pecl input d7, c6 high-speed input and complement. d23, nd23 pecl input b5, a4 high-speed input and complement. d24, nd24 pecl input b4, a3 high-speed input and complement. d25, nd25 pecl input d5, c4 high-speed input and complement. d26, nd26 pecl input d2, e3 high-speed input and complement. d27, nd27 pecl input d1, e2 high-speed input and complement. d28, nd28 pecl input f3, g4 high-speed input and complement. d29, nd29 pecl input e1, f2 high-speed input and complement. d30, nd30 pecl input g3, h4 high-speed input and complement. d31, nd31 pecl input g2, g1 high-speed input and complement. (continued on next page)
TQ8033 14 data sheet for additional information and latest specifications, see our website: www.triquint.com table 7. pin descriptions (cont.) signal type grid ref. description data inputs (cont.) d32, nd32 pecl input w2, y1 high-speed input and complement. d33, nd33 pecl input y2, aa1 high-speed input and complement. d34, nd34 pecl input w4, y3 high-speed input and complement. d35, nd35 pecl input aa4, y5 high-speed input and complement. d36, nd36 pecl input ac3, ab4 high-speed input and complement. d37, nd37 pecl input ac4, ab5 high-speed input and complement. d38, nd38 pecl input aa6, y7 high-speed input and complement. d39, nd39 pecl input ac5, ab6 high-speed input and complement. d40, nd40 pecl input aa7, y8 high-speed input and complement. d41, nd41 pecl input ab7, ac7 high-speed input and complement. d42, nd42 pecl input aa8, ab8 high-speed input and complement. d43, nd43 pecl input aa9, ab9 high-speed input and complement. d44, nd44 pecl input y10, aa10 high-speed input and complement. d45, nd45 pecl input ab10, ac10 high-speed input and complement. d46, nd46 pecl input y11, aa11 high-speed input and complement. d47, nd47 pecl input ab11, ac11 high-speed input and complement. d48, nd48 pecl input aa12, ab12 high-speed input and complement. d49, nd49 pecl input ac13, ab13 high-speed input and complement. d50, nd50 pecl input aa13, y13 high-speed input and complement. d51, nd51 pecl input ac14, ab14 high-speed input and complement. d52, nd52 pecl input aa14, y14 high-speed input and complement. d53, nd53 pecl input ab15, aa15 high-speed input and complement. d54, nd54 pecl input ab16, ac17 high-speed input and complement. d55, nd55 pecl input y16, aa17 high-speed input and complement. d56, nd56 pecl input ab18, ac19 high-speed input and complement. d57, nd57 pecl input y17, aa18 high-speed input and complement. d58, nd58 pecl input ab19, ac20 high-speed input and complement. d59, nd59 pecl input ab20, ac21 high-speed input and complement. d60, nd60 pecl input y19, aa20 high-speed input and complement. d61, nd61 pecl input y21, w20 high-speed input and complement. d62, nd62 pecl input aa23, y22 high-speed input and complement. d63, nd63 pecl input y23, w22 high-speed input and complement. (continued on next page)
TQ8033 15 switching products data sheet for additional information and latest specifications, see our website: www.triquint.com table 7. pin descriptions (cont.) signal type grid ref. description data outputs o0,no0 pecl output h3,h2 high-speed output and complement. o0 and no0 are addressed by oadd = 00000. o31 and no31 are addressed by oadd = 11111. o1, no1 pecl output j3, j2 high-speed output and complement. o2, no2 pecl output k4, k3 high-speed output and complement. o3, no3 pecl output k2, k1 high-speed output and complement. o4, no4 pecl output l4, l3 high-speed output and complement. o5, no5 pecl output l2, l1 high-speed output and complement. o6, n06 pecl output m3, m2 high-speed output and complement. o7, no7 pecl output n1, n2 high-speed output and complement. o8, no8 pecl output n3, n4 high-speed output and complement. o9, no9 pecl output p1, p2 high-speed output and complement. o10, no10 pecl output p3, p4 high-speed output and complement. o11, no11 pecl output r2, r3 high-speed output and complement. o12, no12 pecl output t2, u1 high-speed output and complement. o13, no13 pecl output t4, u3 high-speed output and complement. o14, no14 pecl output v2, w1 high-speed output and complement. o15, no14 pecl output u4, v3 high-speed output and complement. o16, no16 pecl output j22, j21 high-speed output and complement. o17, no17 pecl output k21, k20 high-speed output and complement. o18, no18 pecl output k23, k22 high-speed output and complement. o19, no19 pecl output l21, l20 high-speed output and complement. o20, no20 pecl output l23, l22 high-speed output and complement. o21, no21 pecl output m21, m22 high-speed output and complement. o22, no22 pecl output n22, n23 high-speed output and complement. o23, no23 pecl output n20, n21 high-speed output and complement. o24, no24 pecl output p22, p23 high-speed output and complement. o25, no25 pecl output p20, p21 high-speed output and complement. o26, no26 pecl output r21, r22 high-speed output and complement. o27, no27 pecl output t21, t22 high-speed output and complement. o28, no28 pecl output u22, u23 high-speed output and complement. o29, no29 pecl output u21, t20 high-speed output and complement. o30, no30 pecl output w23, v22 high-speed output and complement. o31, no31 pecl output v21, u20 high-speed output and complement. o32, no32 pecl output h22, g23 high-speed monitor output and complement.
TQ8033 16 data sheet for additional information and latest specifications, see our website: www.triquint.com 17 11 10 9 16 15 14 13 12 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u nc (not connected) = 23 22 21 20 19 18 23 22 21 20 19 18 v w y aa ab ac no28 o27 no27 o26 no26 no25 o24 no24 o22 o23 no22 o21 no21 no19 o19 no20 no17 o17 o18 no16 o16 oadd4 o32 oadd2 oadd1 oadd3 oadd0 iadd5 iadd4 iadd3 iadd2 iadd1 iadd0 nd62 d62 load config o28 no29 o29 no31 o30 o31 nd63 d22 nd22 nd23 d23 d24 nd24 nd25 d25 d26 nd26 d27 nd27 d28 nd28 nd29 d29 d30 nd30 d31 nd31 no0 o0 o1 no1 o2 no2 o3 no3 o4 no4 o5 no5 o6 no6 o7 no7 o8 no8 o9 no9 o10 no10 o11 no11 o12 no12 o14 no14 o15 no15 o13 no13 d32 nd32 d33 nd33 d34 nd34 d35 nd35 d36 nd36 d37 nd37 d38 nd38 nd19 d19 nd18 d18 nd17 d17 nd16 d16 d15 nd14 d14 nd13 nd12 d13 nd11 d12 nd9 d10 d9 nd8 d8 nd7 d7 nd6 d5 nd4 d4 nd3 nd2 d2 nd1 d1 nd59 d59 nd58 d58 nd56 d56 nd55 d55 nd54 d54 nd53 d53 d52 nd51 nd50 d50 nd49 d49 nd48 d48 nd47 d47 nd45 d45 nd44 d44 nd43 d43 nd42 d42 nd41 d41 d20 nd15 d11 nd5 nd0 d60 d57 nd52 d46 nd40 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc dnc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vcc TQ8033 304-pin sbga top view resetin monitor_ld d0 d3 d6 nd10 nd20 d21 nd21 d39 nd39 d40 nd46 d51 nd57 nd60 d61 nd61 d63 no18 o20 no23 o25 no30 no32 dnc (do not connect. leave open) = 17 11 10 9 16 15 14 13 12 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac figure 8. pin assignment - top view
TQ8033 17 switching products data sheet for additional information and latest specifications, see our website: www.triquint.com figure 9. sbga mechanical dimensions table 8. sbga dimensions (in millimeters) symbol parameter min. nom. max. a overall thickness 1.70 a 1 ball height 0.50 0.60 0.70 a 2 body thickness 0.85 0.91 1.00 d body size 31.00 d 1 ball footprint 27.84 27.94 28.04 e body size 31.00 e 1 ball footprint 27.84 27.94 28.04 m,n ball matrix 23 x 23 m1 number of rows 4 b ball diameter 0.60 0.75 0.90 d distance encapsulation to balls 0.5 e ball pitch 1.27 ddd coplanarity 0.15 0.30 0.35 ccc encapsulation height 0.20 t metal back thickness 0.050 0.125 0.175 s solder ball placement 0.00 pcb pad size 0.63
TQ8033 18 data sheet for additional information and latest specifications, see our website: www.triquint.com ordering information TQ8033 1.5 gbit/sec 64x33 crosspoint switch additional information for latest specifications, additional product information, worldwide sales and distribution locations, and information about triquint: web: www.triquint.com tel: (503) 615-9000 email: sales@tqs.com fax: (503) 615-8900 for technical questions and additional information on specific applications: email: applications@tqs.com the information provided herein is believed to be reliable; triquint assumes no liability for inaccuracies or omissions. triqui nt assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. prices and s pecifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any th ird party. triquint does not authorize or warrant any triquint product for use in life-support devices and/or systems. copyright ? 1998 triquint semiconductor, inc. all rights reserved. revision 1.0.a november 1999 thermal management most applications will require the use of a heatsink or other thermal management system in order to keep the package case temperature within the recommended operation limits. as long as the package case temperature does not exceed 85 degrees c, the die temperature will remain well within triquints requirements for reliability. selection of a thermal management device is very dependent on the system mechanical and environmental constrains. several vendors of heatsink and other thermal management systems support the TQ8033s thermally enhanced ball grid array package. these vendors will work with you to evaluate the system requirements and recommend the best solution. heat sink vendors aavid thermal technologies one kool path p.o. box 400 laconia, nh 03247 603-528-3400 sumitomo metal (smi) 2953 bunker hill lane santa clara, ca 95054 408-982-0990 wakefield engineering, inc. 60 audubon road wakefield, ma 01880 617-345-5900

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